Samsung Unveils zHBM Concepts and 400-Plus-Layer BV-NAND: Is AI Memory Going 3D?

What Samsung’s FMS 2026 roadmap means for HBM, NAND, enterprise storage and advanced packaging

Samsung Electronics has introduced a new vision for AI memory: instead of placing high-bandwidth memory beside an AI accelerator, why not stack it directly above the processor?

At FMS 2026 in Santa Clara, Samsung presented zHBM and zNAND-O concept models, along with a V10 Bonding V-NAND prototype featuring more than 400 layers. The announcement suggests that the next phase of AI memory competition may involve much more than increasing HBM speed or stacking additional memory dies.

The larger strategic idea is to shorten the physical distance between compute, memory and storage—and to optimize them as one system.

But the distinction between a technology roadmap and a commercial product is essential. Samsung has not announced a zHBM customer, a sample-shipment schedule, a mass-production date or independently verified benchmark results. Its most eye-catching figures—including approximately eight times the performance of HBM5—are company projections for a future interface system, not measured results from a shipping product.

The announcement therefore matters, but for a different reason than the headline numbers imply. It shows where Samsung believes AI system architecture could move next. It does not yet prove that the company has achieved a commercial breakthrough.

Key Takeaways

• Samsung unveiled a V10 BV-NAND prototype with more than 400 layers and zHBM and zNAND-O concept models at FMS 2026.

• Conventional HBM is generally positioned beside an AI processor; Samsung’s zHBM concept would stack memory directly above the accelerator.

• Samsung says the architecture is intended to shorten data movement and improve bandwidth and power efficiency.

• The company projects that a future zHBM-based interface system could deliver approximately 8 times the performance of HBM5, while wafer bonding could enable more than 10 times the memory density, up to 3 times the energy efficiency and more than a 50% reduction in thermal resistance.

• Those figures are Samsung’s projections, not independent benchmarks of a mass-produced device.

• Commercial validation will require customer samples, external testing, acceptable yield, thermal reliability, competitive cost and a credible production schedule.

1. What Samsung Actually Unveiled at FMS 2026

Samsung’s announcement covered several technologies at different stages of development. Treating them all as finished products would be misleading.

The most tangible new device was V10 BV-NAND, which Reuters described as a prototype. It contains more than 400 layers and uses a wafer-bonding architecture. Samsung said the design increased memory density by approximately 58% compared with its previous V9 generation, while also improving read, write, input/output performance and power efficiency.

The company also presented zHBM and zNAND-O as concept models. zHBM is a proposed architecture for vertically integrating HBM with an AI accelerator. zNAND-O is a high-performance NAND concept under development in four- and eight-layer versions for space-constrained, low-latency edge-AI applications.

Samsung displayed these concepts alongside a broader portfolio that included HBM4E, an HBM5 model, LPDDR5X-PIM and enterprise-storage products such as PM1763 and BM1773.

This combination matters. Samsung is not presenting zHBM as an isolated memory chip. It is positioning the concept within a wider roadmap spanning DRAM, NAND, enterprise SSDs, foundry manufacturing and advanced packaging.

2. Product, Prototype or Concept?

Semiconductor announcements can describe very different levels of technological maturity.

Stage	What It Usually Means	Samsung Technology in This Announcement
Concept	An architectural idea or development direction	zHBM, zNAND-O
Prototype	A physical implementation used to demonstrate feasibility	V10 BV-NAND
Customer sample	Hardware delivered for evaluation and qualification	Not announced for zHBM or V10 BV-NAND
Qualified product	A design that has passed a customer’s technical requirements	Not announced
Mass production	Repeatable manufacturing at commercial yield and cost	Not announced

That distinction is central to interpreting Samsung’s performance claims.

According to Samsung’s official announcement, a next-generation interface system incorporating zHBM is expected to deliver approximately eight times the performance of HBM5. Samsung also says future wafer-bonding technology could enable more than ten times the memory density, triple energy efficiency and reduce thermal resistance by more than half.

These are ambitious architecture targets. They are not independent test results, and Samsung has not disclosed enough detail about the comparison system, workload or interface to reproduce them.

The accurate interpretation is therefore: Samsung is projecting what a future zHBM system may achieve—not reporting what a commercial zHBM product has already achieved.

3. How Conventional HBM Is Arranged

HBM is already a three-dimensional memory technology. Multiple DRAM dies are vertically stacked and linked with through-silicon vias, creating a wide interface capable of moving large amounts of data efficiently.

In many current AI accelerator packages, however, those HBM stacks sit beside the GPU or accelerator on an interposer or other advanced package. This is much closer than placing memory on a separate module, but data must still travel laterally between the processor and HBM.

That arrangement has worked well enough to make HBM a critical component of modern AI systems. Yet as models, context windows and inference workloads expand, the cost of moving data becomes increasingly important.

The bottleneck is no longer just how fast an accelerator can calculate. It is also how quickly and efficiently data can reach the compute engine.

4. What Makes zHBM Different?

Samsung’s zHBM concept changes the physical placement of memory. Instead of locating HBM beside the AI processor, it proposes stacking HBM directly above the accelerator.

The intended benefit is straightforward: a shorter data path could support greater bandwidth, lower latency and better energy efficiency. Samsung also proposes an intermediate layer capable of integrating customer-specific intellectual property, potentially allowing the memory and accelerator to be co-designed for a particular workload.

This would expand the role of a memory supplier. Rather than delivering a standardized HBM stack, the supplier could become more deeply involved in accelerator design, packaging and system optimization.

That opportunity also creates dependence. A customized vertical architecture would require close cooperation among the accelerator designer, memory producer, foundry, packaging provider, test ecosystem and cooling specialists. The more tightly integrated the system becomes, the harder it may be to substitute one component without redesigning the package.

5. Why Data Movement Matters in AI Systems

Moving data consumes time and power. An AI accelerator can remain underutilized if the required parameters, activations or other data do not arrive fast enough.

This is one reason HBM became so valuable: it provides much higher bandwidth than conventional off-package memory. But increasing standalone HBM specifications cannot eliminate every system bottleneck.

Physical distance, interface design, packaging density and thermal limits all influence realized performance. Reducing the distance between compute and memory could improve system efficiency, but only if the package can manage the resulting heat and maintain reliable connections at high manufacturing yield.

Training and inference also create different demands. Training requires large, repeated data transfers and high memory bandwidth. Inference must serve real-time requests, retrieve data and keep latency predictable across large-scale deployments. Both can benefit from faster data access, but their optimal memory and storage configurations may differ.

For that reason, Samsung’s “eight times” projection should be treated as a system-level design target, not as a universal speed comparison between zHBM and all conventional HBM products.

6. What 400-Plus-Layer V10 BV-NAND Changes

Samsung’s V10 BV-NAND is closer to a conventional product-development path than zHBM because a prototype has been shown, but key commercial details remain undisclosed.

The device extends vertical NAND beyond 400 layers and uses wafer bonding. In a bonding architecture, major device sections can be manufactured separately and then joined, allowing engineers to optimize memory-cell and peripheral-circuit structures more independently than in a fully sequential process.

Samsung says V10 increases memory density by approximately 58% over V9. Greater density can place more storage capacity into a given physical area, which may support higher-capacity enterprise SSDs and improve cost or power efficiency if manufacturing yield is sufficiently high.

The qualifier is important. More layers and higher density do not automatically produce better economics. Bonding alignment, defect control, wafer handling, testing and yield determine how much usable output a manufacturer obtains from each wafer.

The prototype is therefore a meaningful technical milestone, but not yet evidence of profitable volume production.

7. Why NAND Matters in the AI Inference Era

AI infrastructure is often discussed as if only GPUs and HBM matter. In practice, AI systems also need large amounts of persistent storage.

Models, training data, embeddings, checkpoints, retrieval databases, logs and frequently accessed content must be stored somewhere. As AI moves from model training toward real-time services, systems may need to retrieve and process large datasets with low and predictable latency.

Enterprise SSDs can sit between slower storage tiers and expensive high-speed memory. Better NAND density, latency and energy efficiency could make that storage layer more capable.

This does not mean AI inference will automatically create unlimited NAND demand. The commercial effect depends on several measurable variables:

• Hyperscaler and enterprise SSD orders

• NAND bit shipments and average selling prices

• Data-center storage capacity per accelerator

• Customer inventory levels

• The balance between new supply and demand

• The extent to which workloads use local flash, pooled storage or alternative architectures

Reuters reported that expanding AI inference workloads have increased demand for high-capacity NAND. Investors should still look for confirmation in orders, shipments and pricing rather than assume that every AI investment produces the same storage demand.

8. Samsung’s Integrated AI Memory Strategy

Samsung’s potential advantage is not proven leadership in zHBM. It is the breadth of capabilities the company can bring to an integrated system.

Samsung operates across:

• DRAM and HBM

• NAND flash

• Enterprise SSDs

• Logic foundry manufacturing

• Advanced packaging

• Memory technologies with in-memory processing

If customers increasingly want compute, memory and packaging to be co-optimized, that portfolio could support a one-stop development model. It may shorten coordination across suppliers and give Samsung more control over the manufacturing stack.

But vertical integration is not automatically superior. Customers may prefer best-in-class components from different vendors. They may also resist becoming dependent on one supplier for memory, logic manufacturing and packaging.

Samsung’s integrated structure becomes a competitive advantage only if it produces better performance, faster development, reliable delivery or lower total cost for customers.

9. The Commercialization Challenges

Stacking more components vertically can reduce data-travel distance, but it concentrates engineering risks.

Thermal management: AI accelerators and HBM both generate heat. Placing memory directly above the processor could create difficult heat-removal paths, even if the bonding interface itself reduces thermal resistance.

Bonding yield: Vertical integration requires precise alignment and reliable interconnections. A defect in one layer can affect the value of the larger package.

Testing: Highly integrated packages can be harder to test before final assembly. Manufacturers must identify failures early enough to avoid combining expensive known-good components with defective ones.

Repairability and product yield: When compute and memory are tightly bonded, replacing a single failed element may be impractical. The economic loss from one defect can therefore increase.

Manufacturing cost: Additional bonding, thinning, inspection, thermal and packaging steps must create enough performance value to justify their cost.

Standards and ecosystem support: A new architecture needs interfaces, design tools, testing methods and customer cooperation. A technically promising design can remain niche if the surrounding ecosystem does not adopt it.

These are not minor implementation details. They determine whether zHBM can move from a concept to a repeatable commercial product.

10. What Would Confirm a Real Competitive Breakthrough?

The next meaningful evidence will not be another architectural rendering. It will be progress through the commercialization sequence.

Investors and industry observers should watch for:

1. A physical zHBM prototype or customer sample

2. A named accelerator partner or joint-development program

3. External benchmarks with disclosed workloads and comparison systems

4. Thermal, reliability and endurance data

5. Bonding yield and manufacturing-cost evidence

6. A customer-qualification and mass-production timetable

7. V10 BV-NAND adoption in enterprise SSD products

8. Orders, shipments and revenue contribution

Until several of these appear, the strongest claims about market leadership remain premature.

It is also important not to misread existing partnerships. Samsung’s previously announced work with accelerator companies in HBM, DDR5 or foundry manufacturing does not mean those customers have adopted zHBM.

11. Competitive Implications for SK Hynix, Micron and Kioxia

Samsung’s announcement broadens the strategic question for the memory industry, but it does not reset the current competitive ranking by itself.

SK Hynix: Its present HBM position should be assessed through customer relationships, qualification, volume production and delivery. Samsung’s future architecture does not erase those commercial strengths. The relevant question is how SK Hynix and its partners respond if vertical compute-memory integration gains customer support.

Micron: Micron competes in DRAM, HBM and NAND and can pursue system-level optimization with major U.S. AI customers. Its next-generation HBM sampling, qualification and packaging partnerships will remain the most useful indicators.

Kioxia: Samsung’s 400-plus-layer V10 BV-NAND places attention on NAND density, wafer bonding and enterprise storage. Kioxia’s response should be judged through its own layer roadmap, bonding strategy, SSD products and manufacturing economics.

Packaging and equipment suppliers: More complex bonding and vertical integration could increase demand for wafer bonding, alignment, thinning, inspection, metrology, testing and thermal-management technologies. However, Samsung has not disclosed zHBM suppliers or a related capital-spending program. Technical relevance alone is not evidence of an equipment order.

The industry may ultimately support several architectures. Conventional HBM, advanced interposers, chiplets, hybrid bonding and vertically integrated memory could coexist across different workloads and price points.

12. Conclusion: A New Architecture, Not Yet a Proven Business

Samsung’s FMS 2026 announcement is significant because it reframes the AI memory race.

The competition may no longer be limited to which company offers the fastest HBM stack or the highest NAND layer count. It may increasingly depend on how effectively suppliers integrate compute, memory, storage, foundry processes and advanced packaging into a manufacturable system.

Samsung is unusually positioned to present that broad vision. V10 BV-NAND demonstrates progress toward higher-density bonded NAND, while zHBM proposes a more radical change in the placement of memory relative to the AI accelerator.

But the evidence must be classified correctly.

• Confirmed: Samsung showed a 400-plus-layer V10 BV-NAND prototype and zHBM and zNAND-O concept models.

• Company projections: A future zHBM system could provide approximately eight times HBM5 performance, more than ten times memory density, up to three times energy efficiency and more than a 50% reduction in thermal resistance.

• Not yet confirmed: Customer adoption, independent performance, production yield, commercial cost, mass-production timing and revenue.

The most defensible conclusion is that Samsung has presented a credible direction for next-generation AI memory architecture, but not yet a proven commercial transition.

Does Samsung’s zHBM concept represent the next commercial step in AI memory—or is the industry still years away from viable 3D integration?

This article is for informational purposes only and does not constitute investment advice.

FAQ

What Is Samsung zHBM?

Samsung zHBM is a concept architecture that would stack high-bandwidth memory directly above an AI accelerator rather than positioning HBM beside the processor. Its goal is to shorten data movement and improve system bandwidth and power efficiency.

Is Samsung zHBM in Mass Production?

No. Samsung described zHBM as a concept model at FMS 2026. The company has not announced customer samples, qualification or a mass-production date.

Is zHBM Really Eight Times Faster Than HBM5?

Samsung projects that a next-generation interface system incorporating zHBM could deliver approximately eight times the performance of HBM5. This is not an independent benchmark of a shipping product, and the company has not disclosed enough information to treat it as a universal chip-to-chip comparison.

What Is V10 BV-NAND?

V10 BV-NAND is Samsung’s prototype Bonding V-NAND architecture with more than 400 layers. Samsung says wafer bonding increases memory density by approximately 58% compared with V9 and improves performance and power efficiency.

Does zHBM Mean Samsung Has Overtaken SK Hynix?

No. A concept roadmap cannot be compared directly with current customer qualifications, production yields and commercial shipments. Samsung’s future architecture and SK Hynix’s present HBM execution should be evaluated separately.

Why Is NAND Important for AI?

AI systems require persistent storage for models, datasets, embeddings, checkpoints and retrieval databases. Higher-capacity, lower-latency enterprise SSDs may benefit from AI infrastructure growth, but demand must be confirmed through orders, shipments and pricing.